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Fault-tolerant error correction using flags and error weight parities

June 8, 2021 - 4:00pm
Theerapat Tansuwannont
University of Waterloo

Fault-tolerant error correction (FTEC), a procedure which suppresses error propagation in a quantum circuit, is one of the most important components for building large-scale quantum computers. One major technique often used in recent works is the flag technique, which uses a few ancillas to detect faults that can lead to errors of high weight and is applicable to various fault-tolerant schemes. In this talk, I will further improve the flag technique by introducing the use of error weight parities in error correction. The new technique is based on the fact that for some families of codes, errors of different weights are logically equivalent if they correspond to the same syndrome and the same error weight parity, and need not be distinguished from one another. I will also give a brief summary of my works on FTEC protocols for several families of codes, including cyclic CSS codes, concatenated Steane code, and capped color codes, which requires only a few ancillas.

Meeting ID: 951 0472 7535

Passcode: mJ8fVht

This talk is part of the IQC-QuICS Math and Computer Science Seminar.