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Surface code error correction on a defective lattice Shota Nagayama et al.

October 17, 2016 -
2:00pm to 3:00pm
Speaker: 
Rodney Van Meter
Institution: 
Keio University

The yield of physical qubits fabricated in the laboratory is much lower than that of classical transistors in production semiconductor fabrication. Actual implementations of quantum computers will be susceptible to loss in the form of physically faulty qubits. Though these physical faults must negatively affect the computation, we can deal with them by adapting error correction schemes. In this paper We have simulated statically placed single-fault lattices and lattices with randomly placed faults at functional qubit yields of 80%, 90% and 95%, showing practical performance of a defective surface code by employing actual circuit constructions and realistic errors on every gate, including identity gates. We extend Stace et al.'s superplaquettes solution against dynamic losses for the surface code to handle static losses such as physically faulty qubits. The single-fault analysis shows that a static loss at the periphery of the lattice has less negative effect than a static loss at the center. The randomly-faulty analysis shows that 95% yield is good enough to build a large scale quantum computer. The local gate error rate threshold is ∼0.3%, and a code distance of seven suppresses the residual error rate below the original error rate at p=0.1%. 90% yield is also good enough when we discard badly fabricated quantum computation chips, while 80% yield does not show enough error suppression even when discarding 90% of the chips. We evaluated several metrics for predicting chip performance, and found that the depth of the deepest stabilizer circuit in the lattice gave the strongest correlation with post-correction residual error rates. Our analysis will help with selecting usable quantum computation chips from among the pool of all fabricated chips.

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Rodney Van Meter received a B.S. in engineering and applied science from the California Institute of Technology in 1986, an M.S. in computer engineering from the University of Southern California in 1991, and a Ph.D. in computer science from Keio University in 2006.

He has held positions in both industry and academia in both the U.S. and Japan.  His current research centers on quantum computer architecture and quantum networking.  Other research interests include storage systems, networking, and post-Moore's Law computer architecture.  He is now an Associate Professor of Environment and Information Studies at Keio University's Shonan Fujisawa Campus.

Dr. Van Meter is a member of AAAS, ACM, IEEE and IPSJ.

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